Entire domain basis function expansion of the differential surface admittance for efficient broadband characterization of lossy interconnects

This article presents a full-wave method to characterize lossy conductors in an interconnect setting. To this end, a novel and accurate differential surface admittance operator for cuboids based on entire domain basis functions is formulated. By combining this new operator with the augmented electric field integral equation, a comprehensive broadband characterization is obtained. Compared with the state of the art in differential surface admittance operator modeling, we prove the accuracy and improved speed of the novel formulation. Additional examples support these conclusions by comparing the results with commerical software tools and with measurements

Impact of gate-level clustering on automated system partitioning of 3D-ICs

When partitioning gate-level netlists using graphs, it is beneficial to cluster gates to reduce the order of the graph and preserve some characteristics of the circuit that the partitioning might degrade. Gate clustering is even more important for netlist partitioning targeting 3D system integration. In this paper, we make the argument that the choice of clustering method for 3D-ICs partitioning is not trivial and deserves careful consideration. To support our claim, we implemented three clustering methods that were used prior to partitioning two synthetic designs representing two extremes of the circuits medium/long interconnect diversity spectrum. Automatically partitioned netlists are then placed and routed in 3D to compare the impact of clustering methods on several metrics. From our experiments, we see that the clustering method indeed has a different impact depending on the design considered and that a circuit-blind, universal partitioning method is not the way to go, with wire-length savings of up to 31%, total power of up to 22%, and effective frequency of up to 15% compared to other methods. Furthermore, we highlight that 3D-ICs open new opportunities to design systems with a denser interconnect, drastically reducing the design utilization of circuits that would not be considered viable in 2D.Comment: 8 pages, 6 figure

Insertion Bonding: A Novel Cu-Cu Bonding Approach for 3D Integration

Abstract A novel low temperature Cu-Cu bonding approach called the insertion bonding technique has been developed. This technique leverages on the initiation of high shear stresses at metal-metal contact interface, thus resulting in high plastic deformation, which is essential for strong bond formation. Through finite element studies, it is observed that the insertion bonding technique result in significantly larger plastic deformation in comparison to the conventional bonding technique under the same bonding conditions. Experimental studies of the insertion bonding technique were performed and it is observed that a seamless bond interface is achieved, even at a low bonding temperature of 100°C. Bonding at room temperature (RT) in the presence of a surface cleaning agent resulted in an improved bond interface. Resistance measurement of the samples bonded at 100°C revealed that an electrical contact is achieved between the stacked dies. This shows that the insertion bonding techniques holds much promise for low temperature Cu-Cu bonding

NimbleAI: towards neuromorphic sensing-processing 3D-integrated chips

The NimbleAI Horizon Europe project leverages key principles of energy-efficient visual sensing and processing in biological eyes and brains, and harnesses the latest advances in 33D stacked silicon integration, to create an integral sensing-processing neuromorphic architecture that efficiently and accurately runs computer vision algorithms in area-constrained endpoint chips. The rationale behind the NimbleAI architecture is: sense data only with high information value and discard data as soon as they are found not to be useful for the application (in a given context). The NimbleAI sensing-processing architecture is to be specialized after-deployment by tunning system-level trade-offs for each particular computer vision algorithm and deployment environment. The objectives of NimbleAI are: (1) 100x performance per mW gains compared to state-of-the-practice solutions (i.e., CPU/GPUs processing frame-based video); (2) 50x processing latency reduction compared to CPU/GPUs; (3) energy consumption in the order of tens of mWs; and (4) silicon area of approx. 50 mm 2 .NimbleAI has received funding from the EU’s Horizon Europe Research and Innovation programme (Grant Agreement 101070679), and by the UK Research and Innovation (UKRI) under the UK government’s Horizon Europe funding guarantee (Grant Agreement 10039070)Peer ReviewedArticle signat per 49 autors/es: Xabier Iturbe, IKERLAN, Basque Country (Spain); Nassim Abderrahmane, MENTA, France; Jaume Abella, Barcelona Supercomputing Center (BSC), Catalonia, Spain; Sergi Alcaide, Barcelona Supercomputing Center (BSC), Catalonia, Spain; Eric Beyne, IMEC, Belgium; Henri-Pierre Charles, CEA-LIST, University Grenoble Alpes, France; Christelle Charpin-Nicolle, CEALETI, Univ. Grenoble Alpes, France; Lars Chittka, Queen Mary University of London, UK; Angélica Dávila, IKERLAN, Basque Country (Spain); Arne Erdmann, Raytrix, Germany; Carles Estrada, IKERLAN, Basque Country (Spain); Ander Fernández, IKERLAN, Basque Country (Spain); Anna Fontanelli, Monozukuri (MZ Technologies), Italy; José Flich, Universitat Politecnica de Valencia, Spain; Gianluca Furano, ESA ESTEC, Netherlands; Alejandro Hernán Gloriani, Viewpointsystem, Austria; Erik Isusquiza, ULMA Medical Technologies, Basque Country (Spain); Radu Grosu, TU Wien, Austria; Carles Hernández, Universitat Politecnica de Valencia, Spain; Daniele Ielmini, Politecnico Milano, Italy; David Jackson, University of Manchester, UK; Maha Kooli, CEA-LIST, University Grenoble Alpes, France; Nicola Lepri, Politecnico Milano, Italy; Bernabé Linares-Barranco, CSIC, Spain; Jean-Loup Lachese, MENTA, France; Eric Laurent, MENTA, France; Menno Lindwer, GrAI Matter Labs (GML), Netherlands; Frank Linsenmaier, Viewpointsystem, Austria; Mikel Luján, University of Manchester, UK; Karel Masařík, CODASIP, Czech Republic; Nele Mentens, Universiteit Leiden, Netherlands; Orlando Moreira, GrAI Matter Labs (GML), Netherlands; Chinmay Nawghane, IMEC, Belgium; Luca Peres, University of Manchester, UK; Jean-Philippe Noel, CEA-LIST, University Grenoble Alpes, France; Arash Pourtaherian, GrAI Matter Labs (GML), Netherlands; Christoph Posch, PROPHESEE, France; Peter Priller, AVL List, Austria; Zdenek Prikryl, CODASIP, Czech Republic; Felix Resch, TU Wien, Austria; Oliver Rhodes, University of Manchester, UK; Todor Stefanov, Universiteit Leiden, Netherlands; Moritz Storring, IMEC, Belgium; Michele Taliercio, Monozukuri (MZ Technologies), Italy; Rafael Tornero, Universitat Politecnica de Valencia, Spain; Marcel van de Burgwal, IMEC, Belgium; Geert van der Plas, IMEC, Belgium; Elisa Vianello, CEALETI, Univ. Grenoble Alpes, France; Pavel Zaykov, CODASIP, Czech RepublicPostprint (author's final draft

Analytical thermo-mechanical model for non-underfilled area array flip chip assemblies

An analytical model is derived for the calculation of thermo-mechanical induced stresses in area array flip chip assemblies. This analytical model is based on structural mechanics and has the ability to characterize the nature and to estimate the magnitude of the induced stresses. The extension of this model compared to existing procedures is its applicability to area array systems, which behave significantly different from peripheral assemblies. The model is compared to finite element simulations. The model calculates accurately the forces and bending moments acting on the flip chip connections. The transformation of these forces and moments into stresses is less accurate as the model does not include stress concentrations near the corners. The model simulates very well the different parameter trends such as chip size and is therefore well suited for understanding parameter sensitivity studies.status: publishe

Numerically efficient spatial-domain moment method for multislot transmission lines in layered media - Application to multislot lines in MCM-D technology

status: publishe